1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to a chip on glass (COG) type LCD device and an inspecting method of the same.
2. Discussion of the Related Art
With the rapid development in information technology, flat panel display (FPD) devices having thin thickness, light weight, and lower power consumption have been introduced and developed.
Among these devices, liquid crystal display (LCD) devices are most widely used for monitors of notebook computers, monitors of personal computers and televisions due to high definition, high qualities, excellent moving images and high contrast ratio.
An LCD device includes two substrates and a liquid crystal layer interposed between the two substrates. Electrodes are formed on respective substrates, and the substrates are disposed such that the electrodes face each other. An electric field is induced between the electrodes when voltages are applied to the electrodes. The alignment direction of the liquid crystal molecules is controlled by varying the intensity of the electric field, and the transmittance of light through the liquid crystal layer is changed to display images.
FIG. 1 is an exploded perspective view of an LCD device according to the related art. As shown in FIG. 1, the LCD device includes an array substrate 10, a color filter substrate 20 and a liquid crystal layer 30. The array substrate 10 and color filter substrate 20 face each other, and the liquid crystal layer 30 is interposed therebetween.
The array substrate 10 includes gate lines 14 and data lines 16 on an inner surface of a transparent substrate 12. The gate lines 14 and the data lines 16 cross each other such that regions formed between the gate and data lines 14 and 16 are defined as pixel regions P. A thin film transistor Tr is formed at each crossing portion of the gate and data lines 14 and 16, and a pixel electrode 18 is formed in each pixel region P and connected to the thin film transistor Tr.
The color filter substrate 20 includes a black matrix 25, a color filter layer 26, and a common electrode 28 on an inner surface of a transparent substrate 22 facing the array substrate 10. The black matrix 25 has a lattice shape to cover a non-display region such as the gate lines 14, the data lines 16, the thin film transistors Tr, and so on. The color filter layer 26 includes red, green and blue color filter patterns 26a, 26b, and 26c repeatedly arranged in order. Each of the color filter patterns 26a, 26b, and 26c corresponds to each pixel region P. The common electrode 28 is formed on the black matrix 25 and the color filter layers 26 and over an entire surface of the substrate 22.
A sealant (not shown) is formed along peripheries of the array substrate 10 and the color filter substrate 20 to prevent liquid crystal molecules of the liquid crystal layer 30 from leaking. An alignment layer (not shown) is formed between the liquid crystal layer 30 and each of the array substrate 10 and the color filter substrate 20 to determine an initial direction of the liquid crystal molecules. A polarizer (not shown) is disposed on an outer surface of at least one of the array substrate 10 and the color filter substrate 20. A backlight unit (not shown) is disposed on an outer surface of the array substrate 10 to provide lights.
Scan signals for turning on/off the thin film transistors Tr are sequentially applied to the gate lines 14, and data signals are applied to the pixel electrodes 18 in the selected pixel regions P through the data lines 16. An electric field perpendicular to the substrates 12 and 22 is induced between the pixel electrodes 18 and the common electrode 28. The arrangement of the liquid crystal molecules is controlled by the electric field, and the transmittance of light is changed by varying the arrangement of the liquid crystal molecules to thereby display images.
In the LCD device, the array substrate, the color filter substrate and the liquid crystal layer may be defined as a liquid crystal panel. The LCD device further includes a driving unit at a periphery of the liquid crystal panel to drive the liquid crystal panel. The driving unit includes a printed circuit board (PCB), on which elements for generating control signals and data signals are mounted, and driving integrated circuits (ICs), which is connected to the liquid crystal panel and the PCB and is used to apply signals to signal lines of the liquid crystal panel.
The LCD device may be categorized into a chip on glass (COG) type, a tape carrier package (TCP) type and a chip on film (COF) type according to a method of packaging the driving ICs on the liquid crystal panel.
The COG type has a simple structure as compared with the TCP type and the COF type and increases the ratio of the liquid crystal panel in the LCD device. Therefore, recently, the COG type has been widely used for a small-sized LCD device.
In the COG type LCD device, driving ICs are attached to a non-display area of an array substrate. The COG type LCD device is inspected to detect defects before attaching the driving ICs. Accordingly, testing lines and pads are formed in the non-display area of the array substrate.
FIG. 2 is a view of schematically illustrating an inspecting structure of a COG type LCD device according to the related art. FIG. 2 shows testing lines, testing pads and testing thin film transistors.
In FIG. 2, the related art COG type LCD device 50 includes a display area DA and a non-display area substantially surrounding the display area DA. Gate lines GL and data lines DL are formed in the display area DA. Gate link lines GLL1, GLL2, GLL3 and GLL4 are formed in the non-display area at left and right sides of the display area DA in the context of the figure, and the gate link lines GLL1, GLL2, GLL3 and GLL4 are connected to the gate lines GL. Data link lines DLL are formed in the non-display area at a lower side of the display area DA in the context of the figure, and the data link lines DLL are connected to the data lines DL. First, second and third testing transistors ITr1, ITr2 and ITr3 and testing pads IP1 to IP12 are formed in the non-display area. The first, second and third testing transistors ITr1, ITr2 and ITr3 are formed between the gate link lines GLL1, GLL2, GLL3 and GLL4 and the testing pads IP1 to IP12 or between the data link lines DLL and the testing pads IP1 to IP12.
The gate lines GL in the display area DA includes odd gate lines GL1 and GL3 and even gate lines GL2 and GL4. The odd gate lines GL1 and GL3 are alternately connected to first and second gate link lines GLL1 and GLL2 in the non-display area at the left side of the display area DA. The even gate lines GL2 and GL4 are alternately connected to third and fourth gate link lines GLL3 and GLL4 in the non-display area at the right side of the display area DA.
Here, first testing thin film transistors ITr1 are respectively connected to the first and second gate link lines GLL1 and GLL2, and a first gate enable line 60 is connected to gate electrodes of the first testing thin film transistors ITr1 and controls on/off of the first testing thin film transistors ITr1. A first gate enable pad IP3 is connected to the first gate enable line 60. Second testing thin film transistors ITr2 are respectively connected to the third and fourth gate link lines GLL3 and GLL4, and a second gate enable line 62 is connected to gate electrodes of the second testing thin film transistors ITr2 and controls on/off of the second testing thin film transistors ITr2. A second gate enable pad IP4 is connected to the second gate enable line 62.
In addition, first and second gate testing lines 51 and 52 are electrically connected to the first and second gate link lines GLL1 and GLL2 through the first testing thin film transistors ITr1. Third and fourth gate testing lines 53 and 54 are electrically connected to the third and fourth gate link lines GLL3 and GLL4 through the second testing thin film transistors ITr2. First, second, third and fourth gate testing pads IP1, IP2, IP5 and IP6 are disposed at ends of the first, second, third and fourth gate link lines GLL1, GLL2, GLL3 and GLL4, respectively.
In the non-display area at the lower side of the display area DA in the context of the figure, a first data testing line 64 is electrically connected to first data lines DL1, which are connected to red sub-pixels R, through the third testing thin film transistors ITr3 and the data link lines DLL, and a first data testing pad IP8 is connected to the first data testing line 64. A second data testing line 66 is electrically connected to second data lines DL2, which are connected to green sub-pixels G, through the third testing thin film transistors ITr3 and the data link lines DLL, and a second data testing pad IP9 is connected to the second data testing line 66. A third data testing line 68 is electrically connected to the third data lines DL3, which are connected to blue sub-pixels B, through the third testing thin film transistors ITr3 and the data link lines DLL, and a third data testing pad IP10 is connected to the third data testing line 68.
A data enable line 70 is connected to gate electrodes of the third testing thin film transistors ITr3, which are electrically connected to the first, second and third data lines DL1, DL2 and DL3, and controls on/off of the third testing thin film transistors ITr3. A data enable pad IP11 is connected to the data enable line 70.
First and second common link lines 71 and 72 are formed in the non-display area to apply a common voltage to a common electrode (not shown) that is formed on a color filter substrate (not shown). First and second common pads IP7 and IP12 are connected to the first and second common link lines 71 and 72, respectively.
Here, the third testing thin film transistors ITr3 connected to the data link lines DLL are positioned in a region where a driving integrated circuit (IC) is attached.
Voltages are applied to the testing pads IP1 to IP12, and on/off of the first, second and third testing thin film transistors ITr1, ITr2 and ITr3 are controlled. Accordingly, an inspecting process is performed to detect defects of the sub-pixels R, G and B in the display area DA.
However, in the related art COG type LCD device 50, block dim effects, which are caused by a partial difference of brightness in the display area DA, continuously occur when the inspecting process is carried out according to an arrangement of bump pads of the driving IC.
Specially, as shown in FIG. 3, which is an enlarged view of a driving IC region of an array substrate for a COG type LCD device according to the related art, if the COG type LCD device includes a driving IC such that a distance between adjacent bump pads in a central portion is wider than other portions in a region for attaching the driving IC, the block dim effects highly occur during the lighting inspection. In FIG. 3, a vacant space of about 2 mm is shown in the central portion differently from the other portions.
In the related art, the first, second and third testing thin film transistors are non-uniformly dry-etched due to loading effects of the spaces between the bump pads and may have different ratios of channel width to length. Accordingly, the first, second and third testing thin film transistors have different characteristics, and this causes block dim effects during the lighting inspection of the COG type LCD device.
More particularly, to connect the gate and the data lines for the lighting inspection, the gate and data lines are connected to output bump pads, which are disposed in the driving IC region, and connected to the driving IC. The testing lines, the testing pads, and the first, second and third testing thin film transistors are connected to the output bump pads and are disposed between the output bump pads and the input bump pads. At this time, distances between the first, second and third thin film transistors are changed in a portion where the space between the bump pads is wider. There is the difference between the thin film transistors due to the non-uniform etching.
Accordingly, it is difficult to accurately judge whether the block dim effects are caused when the driving IC is attached or are caused when the lighting inspection is performed before attaching the driving IC. Therefore, even though there are the block dim effects during the lighting inspection, the COG type LCD device is determined as a good product. Then, when the block dim effects occur after attaching the driving IC, the COG type LCD device is determined as a bad product and is discarded. This increases the manufacturing costs.